The invention relates to a synchronization device for a semiconductor memory device, in particular a high-frequency semiconductor memory device or a DDR-RAM memory module. In the synchronization device an input clock signal of the semiconductor memory device can be generated or received and then time-modulated. The time-modulated clock signal can be outputted as an output clock signal and provided to the semiconductor memory device for processing.
In semiconductor memory devices, an operation is based on a clock signal that is externally supplied or internally generated. Memory contents in the semiconductor memory device are stored, read, or deleted according to the clock signal. Because semiconductor devices contain a number of storage units, and a plurality of semiconductor memory units are typically jointly utilized in a circuit configurationxe2x80x94particularly according to a common clockxe2x80x94the synchronicity of the respective clock signals relative to one another and to the outputted data must be taken into consideration for the operation and configuration of modern semiconductor devices, so that each write, read, or delete command can be allocated a corresponding item of data which appears at the semiconductor memory device at a specified time, for example.
These aspects are particularly important in high-frequency or high-cycle semiconductor memory devices and particularly double-data-rate semiconductor memory devices such as DDR-RAMs.
Hitherto, the synchronization requirements have been taken into account by the provision of a synchronization device wherein an input clock signal of the semiconductor memory device can be generated or received, the generated or received input clock signal is time-modulatable, and the time-modulated generated or received input clock signal can be outputted as an output clock signal and made available to the semiconductor memory device for processing.
However, it is problematic that the synchronization device must be tuned to the circuit environment. Hitherto, the tuning has been determined and set in the stationary operating state, i.e. for a specified and predetermined operating temperature of the semiconductor memory device or synchronization device. But when the operating temperature of the semiconductor memory device or synchronization device changes, deviations occur in the tuning of the synchronization behavior of the synchronization device relative to the stationary state. This is particularly disadvantageous for operating from a normal mode into an energy-saving mode, and particularly when moving from the energy-saving mode into the normal mode.
It is accordingly an object of the invention to provide a synchronization device for a semiconductor memory device that overcomes the above-mentioned disadvantages of the prior art devices of this general type, with which a clock signal can be time-tuned in a particularly reliable fashion.
With the foregoing and other objects in view there is provided, in accordance with the invention, a synchronization device for a semiconductor memory device. The synchronization device contains a temperature-controllable delay device for assisting in time modulating an input clock signal. The temperature-controllable delay device receives or generates the input clock signal. The temperature-controllable delay device further generates a signal delay dependent on an operating temperature of the semiconductor memory device. The temperature-controllable delay device outputs an output clock signal based on the input clock signal with a delay equal to the signal delay.
The inventive synchronization device is characterized by the provision of a temperature-controllable or temperature-controlled delay device. Furthermore, a signal delay that is dependent on an operating temperature of the semiconductor memory device can be generated by the temperature-controllable or temperature-controlled delay device. Furthermore, the generated or received clock signal can be outputted by the temperature-controllable or temperature-controlled delay device as an output clock signal with a delay equal to the signal delay.
It is thus a core idea of the present invention to provide a delay device inside the synchronization device that is itself temperature-controllable or temperature-controlled. The temperature-controllable or temperature-controlled delay device generates a signal delay relative to the generated or received input clock signal that takes into account the temperature dependency. The signal delay that is generated according to the respective operating temperature of the semiconductor memory device is taken into consideration in that the generated and received input clock signal is released by the temperature-controlled or temperature-controllable delay device as an output clock signal with a delay equal to the generated signal delay.
The signal delay that is generated as a function of temperature is so selected and set, that the following relation for the input clock signal Cin and the output clock signal Cout can be satisfied, or at least approximately so:
Cout(t)=Cin(txe2x88x92xcex94t(xcex8)).
Here, t is time, xcex94t is the signal delay relative to the input clock signals Cin and the output clock signals Cout, and xcex8 is the temperature.
According to the present invention, the temperature-dependent signal delay xcex94t(xcex8) can be generated by the temperature-controlled or temperature-controllable delay device in such a way that the output clock signal Cout or its time characteristic is substantially independent of an operating temperature of the semiconductor memory device.
All the temperature dependencies of the individual portions of particular assemblies that occur in the synchronization device and the semiconductor memory device are taken into account in the overall delay, and the temperature-dependent signal delay xcex94t(xcex8) that is generated by the temperature-controlled or temperature-controllable delay device is adapted so that a signal delay that is constant across all temperatures emerges between the input signal Cin and the output signal Cout for all operating temperatures as a whole for the entire synchronization device and/or for the entire semiconductor memory device including the synchronization device.
In particular, it is provided that a first signal delay xcex94t(xcex8l) and a second signal delay xcex94t(xcex8t2) can be generated for each first operating temperature xcex81 and each second operating temperature xcex82 of the semiconductor memory device, respectively, in such a way that the relation
Cout1(t)=Cout2(t)
can be satisfied, or at least approximately so, by the respective output clock signals Cout1 and Cout2 at all times t, provided that the relation
Cin1(t)=Cin2(t)
is satisfied by the input signals Cin1 and Cin2, or at least approximately so, at all times t.
What this ultimately results in is that the overall delay between the input clock signal Cin and the output clock signal Cout remains constant, regardless of the operating temperature xcex8, because the temperature-dependent xe2x80x9cadditional delayxe2x80x9d xcex94t(xcex8) is increased or decreased accordingly.
In particular, it is provided that a relatively shorter signal delay xcex94t(xcex8) is generated given a relatively higher operating temperature xcex8 of the semiconductor memory device.
Alternatively or in addition, it is provided that a relatively long signal delay xcex94t(xcex8) can be generated given a relatively low operating temperature xcex8 of the semiconductor memory device.
It is provided for purposes of performing the temperature-dependent controlling of the signal delay xcex94t that a temperature signal T that is representative of the respective operating temperature xcex8 of the semiconductor memory device is or can be utilized, particularly in the form of what is known as a control voltage Vcntrl.
The temperature signal T is advantageously suppliable, namely from outside, by a control line that is provided. It is further provided that the temperature signal T can be generated and supplied by a temperature sensor device that is provided.
The temperature sensor is or can be connected to a control line device.
According to a particularly advantageous embodiment of the inventive synchronization device, it is provided that the synchronization device contains a delay line with an input terminal, an output terminal, and a control terminal.
Alternatively or additionally, it is provided that the delay device is disposed with an input terminal and an output terminal in the output terminal of the delay device.
In another alternative of the invention, it is provided that a feedback device with an input terminal and an output terminal is provided. In addition, a phase detector with first and second input terminals and an output terminal is provided.
It is particularly preferable when the input terminal of the feedback device is connected to the output terminal of the delay device in the input terminal of the delay line, and the output terminal of the feedback device is connected to the first input terminal of the phase detector device.
Furthermore, it can be provided that the second input terminal of the phase detector is connected to the input terminal of the delay line, and the output terminal of the phase detector is connected to the control terminal of the delay line.
It is particularly simple and advantageous when, according to another preferred embodiment of the present invention, the delay device contains two in-series tri-state inverters.
According to another aspect of the invention, a semiconductor memory device is provided in which a synchronization device is provided for time-modulating a clock signal, and the synchronization device is configured according to the invention.
These and other aspects of the invention also derive from the following description.
In double-data-rate DRAMS (DDR-RAMs), the data that are read are synchronized with an external clock edge. The phase difference between the external clock signal and the data that are read is thus minimized. The synchronization is performed with the aid of what are known as delay locked loop circuits (DLL). At current-saving drive rates (power down modes), a number of circuit parts and the DLL are shut off. This lowers the temperature of the chip. At the end of the power down mode (power down exit), the phase relation between the external clock signal and the read data is no longer a good match, because the phase difference was minimized in the hot chip and is no longer exactly in tune in the cooler chip. The proposed solution measures the temperature on the chip and adjusts an additional delay element in order to minimize the phase difference following a power down exit.
Hitherto, either the DLL was driven in the power down mode, or an exacerbation of the phase difference following a power down exit was accepted as a trade-off.
The advantages related to the ability to shut off the DLL in the power down mode in order to save current, while nevertheless minimizing the phase difference at the same time.
The invention relates to synchronizing data DQ less than 0:n greater than  with an external clock signal (CLK) with the aid of the DLL. The clock CLK is compared with the output of a feedback circuit (FB) in a phase detector. Inside the feedback circuit, the delay of the receiver (RCV) and the off-chip driver (OCD) is simulated. The delay of the delay line (DL) is adjusted until the phase difference at the input of the phase detector reaches zero.
The following relation exists at the phase detector:
tRCV+tDL+tVCDL+tFB=tRCV+nxc2x7tcyc
where tcyc is the cycle time of the clock signal.
With
tFB=tRCV+tOCD
the same relation exists as the relation between the CLK input and the DQ output
tRCV+tDL+tVCDL+tOCD=nxc2x7tcyc
CLK and DQ less than 0:n greater than  are thus in phase for
tDL=nxc2x7tcycxe2x88x92tOCDxe2x88x92tRCVxe2x88x92tVCDL
tDL is constantly readjusted as long as the chip is not in a power down state in which the DLL is likewise off. In the power down state, the chip cools down and tOCD, TRCV and tDL become shorter. A phase difference between CLK and DQ less than 0:15 greater than  should therefore emerge after the power down exit. The temperature is measured by a temperature sensor (e.g. a bandgap preference circuit that is implemented on each chip) and converted into a control voltage (Vctrl), and the delay of the voltage controlled delay line VCDL is readjusted. The temperature drift of tOCD, tRCV and tDL can be partly compensated by this. This makes it possible to completely shut down the DLL in the power down mode, because it is not necessary to readjust the delay line in the power down mode.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a synchronization device for a semiconductor memory device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.